The invention relates to the general field of semiconductor device manufacturing with particular reference to fabrication of the gate pedestal in a field effect transistor.
The process for manufacturing a field effect transistor includes the steps of laying down a layer of polysilicon over a layer of gate oxide. The polysilicon is then patterned and etched down to the level of the oxide in order to form the gate pedestal. A preferred method for depositing this polysilicon has been the silicon furnace.
Although the silicon furnace is preferred for depositing the polysilicon because of its large saturation current, the surface of the polysilicon that is obtained in this manner is relatively rough. Typical roughness numbers are about 4.5 nm (RMS), associated with a maximum peak-to-valley surface topography of about 24 nm. As the dimensions of semiconductor devices grew smaller and smaller, this degree of roughness could not be tolerated so it has become common practice to smooth out the polysilicon upper surface before proceeding to form the gate pedestal. This is most conveniently done by means of CMP (chemical mechanical polishing).
A problem associated with CMP is a tendency to remove more polysilicon than is necessary because of the difficulty of determining exactly when the polysilicon surface has achieved its maximum level of smoothness. This adds to the cost of the manufacturing process and in some circumstances may even lead to the removal of more polysilicon than was intended. The present invention teaches how no more polysilicon than is absolutely necessary needs to be removed.
A routine search did not uncover any prior art that solves this problem in the manner of the present invention. Several references of interest were, however, encountered. For example, Grewal et al. (U.S. Pat. No. 5,723,381) use a polysilicon layer in sacrificial mode in order to form self-aligned, overlapping bit line contacts. Chau et al. (U.S. Pat. No. 5,434,093) teach the use of CMP to planarize the surface of an oxide filled trench while Kao et al. (U.S. Pat. No. 5,688,700) teach the use of CMP for planarizing gate material but they did not use a sacrificial dielectric layer.
It has been an object of the present invention to provide a process for smoothing the upper surface of a deposited layer of polysilicon.
Another object of the invention has been to minimize the amount of polysilicon that is lost during the smoothing operation.
These objects have been achieved by laying down a thin layer of a dielectric on the surface of polysilicon prior to the application of CMP. This layer serves as a sacrificial layer to facilitate the polishing operation and results in a polysilicon surface that is both very smooth and that has undergone minimum loss of polysilicon.